4 channel 500msps dds with 10-bit dacs preliminary technical data AD9959 rev. prb information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2004 analog devices, inc. all rights reserved. features four synchronized dds channels @500 msps independent frequency / phase / amplitude control between all channels matched latencies for freq, phase, and amplitude changes excellent channel to channel isolation frequency sweeping capability up to 16 levels of modulation (pin selectable) individually programmable dac full scale currents four integrated 10-bit d/a converters(dacs) 32-bit frequency tu ning resolution 14-bit phase offset resolution 10-bit output amplitude scaling resolution serial i/o port(spi) with enhanced data throughput software/hardware controlled power-down dual supply operation (1.8 v dds core / 3.3 v serial i/o) built-in synchronization for multiple devices selectable ref_clk multipier(pll) 4x to 20x (bypassable) selectable ref_clk crystal operation 56 pin lfcsp package applications agile l.o. frequency synthesis phased array radar / sonar instrumentation synchronized clocking rf source for aotf functional block diagram 14 buffer / xtal oscillator clk_mode_sel m u x ref clock multiplier (pll) 4x to 20x channel registers pwr_dwn_ctl ftw phase offset iout dac 4 osc / ref_clk master_reset cs sclk sdio_0 sdio_1 sdio_2 sdio_3 scalable dac ref current dac_rset cos(x) digital multiplier i/o port buffer 10 frequency accumulator 10 10 dac cos(x) 10 10 dac cos(x) 10 10 dac cos(x) 10 10 32 8 ramp rate dftw 32 timing & control logic sync_clk sync_in sync_out profile registers p s 0 p s 3 p s 2 p s 1 system clk i/o_update avdd dvdd dvdd_io 1.8v 1.8v 3.3v 15 32 32 32 32 32 32 32 32 15 15 15 osc / ref_clk dds core dds core dds core dds core control registers iout iout iout iout iout iout iout frequency accumulator frequency accumulator frequency accumulator figure 1 AD9959 block diagram
AD9959 preliminary technical data rev. prb | page 2 of 9 AD9959specifications table 1. unless otherwise noted, avdd, dvdd = 1.8 v 5%, dvdd_i/o = 3.3 v 5%, r set = 1.96 k?, external reference clock frequency = 500 msps (ref_clk multiplier bypassed) parameter min typ max units test conditions/comments ref clock input characteristics ref_clk inputs must be ac coupled due to internal biasing frequency range ref_clk multiplier bypassed 0 500 mhz ref_clk multiplier enabled at 4x(min) 25 125 mhz ref_clk multiplier enabled at 20x(max) 5 25 mhz internal vco range w/ ref_ clk multiplier enabled 100 500 mhz crystal ref_clk source mode 20 30 mhz input power sensitivity -15 3 dbm external 50 ohm termination input voltage level 400 mv input capacitance 3 pf input impedance 1500 ohms duty cycle w/ ref_clk multiplier bypassed 50 % duty cycle w/ ref_clk multiplier enabled 35 65 % clk mode select logic 1 voltage 1.25 v not a 3.3v digital input clk mode select logic 0 voltage 0.6 v not a 3.3v digital input dac output characteristics must be referenced to avdd resolution 10 bits full scale ouput current 10 ma gain error -10 10 %fs output offset 0.6 ua differential nonlinearity -0.5 0.5 lsb integral nonlinearity -1 1 lsb output capactiance 5 pf voltage compliance range avddC 0.50 avdd + 0.50 v channel to channel isolation 60 db channel to channel amplitude matching error 2 % wideband sfdr wideband sfdr defined as dc to nyquist 1-20 mhz analog out -65 dbc 20-60 mhz analog out -62 dbc 60-100 mhz analog out -59 dbc 100-150 mhz analog out -56 dbc 150-200 mhz analog out -54 dbc narrowband sfdr 1.1 mhz analog out (+/- 10khz) -90 dbc 1.1 mhz analog out (+/- 50khz) -88 dbc 1.1 mhz analog out (+/- 250khz) -86 dbc 1.1 mhz analog out (+/- 1mhz) -85 dbc 15.1 mhz analog out (+/- 10khz) -90 dbc 15.1 mhz analog out (+/- 50khz) -87 dbc 15.1 mhz analog out (+/- 250khz) -85 dbc 15.1 mhz analog out (+/- 1mhz) -83 dbc 40.1 mhz analog out (+/- 10khz) -90 dbc 40.1 mhz analog out (+/- 50khz) -87 dbc 40.1 mhz analog out (+/- 250khz) -84 dbc 40.1 mhz analog out (+/- 1mhz) -82 dbc
preliminary technical data AD9959 rev. prb | page 3 of 9 parameter min typ max units test conditions/comments 75.1 mhz analog out (+/- 10khz) -87 dbc 75.1 mhz analog out (+/- 50khz) -85 dbc 75.1 mhz analog out (+/- 250khz) -83 dbc 75.1 mhz analog out (+/- 1mhz) -82 dbc 100.1 mhz analog out (+/- 10khz) -87 dbc 100.1 mhz analog out (+/- 50khz) -85 dbc 100.1 mhz analog out (+/- 250khz) -83 dbc 100.1 mhz analog out (+/- 1mhz) -81 dbc 200.1 mhz analog out (+/- 10khz) -87 dbc 200.1 mhz analog out (+/- 50khz) -85 dbc 200.1 mhz analog out (+/- 250khz) -83 dbc 200.1 mhz analog out (+/- 1mhz) -81 dbc phase noise characteristics residual phase noise @15.1 mhz(aout) @1khz offset tbd dbc/ hz @10khz offset tbd dbc/ hz @100khz offset tbd dbc/ hz @1mhz offset tbd dbc/ hz residual phase noise @ 75.1 mhz(aout) @1khz offset tbd dbc/ hz @10khz offset tbd dbc/ hz @100khz offset tbd dbc/ hz @1mhz offset tbd dbc/ hz residual phase noise @ 200.1 mhz(aout) @1khz offset tbd dbc/ hz @10khz offset tbd dbc/ hz @100khz offset tbd dbc/ hz @1mhz offset tbd dbc/ hz residual phase noise @ 15.1 mhz(aout) w/ ref clk multiplier enabled 4x @1khz offset tbd dbc/ hz @10khz offset tbd dbc/ hz @100khz offset tbd dbc/ hz @1mhz offset tbd dbc/ hz residual phase noise @ 75.1 mhz(aout) w/ ref clk multiplier enabled 4x @1khz offset tbd dbc/ hz @10khz offset tbd dbc/ hz @100khz offset tbd dbc/ hz @1mhz offset tbd dbc/ hz residual phase noise @ 200.1 mhz(aout) w/ ref clk multiplier enabled 4x @1khz offset tbd dbc/ hz @10khz offset tbd dbc/ hz @100khz offset tbd dbc/ hz @1mhz offset tbd dbc/ hz serial port timing characteristics maximum frequency 200 mhz minimum clock pulsewidth low (t pwl ) tbd ns minimum clock pulsewidth high (t pwh ) tbd ns
AD9959 preliminary technical data rev. prb | page 4 of 9 maximum clock rise/fall time tbd ns minimum data setup time (t ds ) tbd ns minimum data hold time tbd ns misc timing characteristics master_reset minimum pulsewidth tbd sync clk i/o_update minimum pulsewidth 1 sync clk minimum setup time (io_update to sync_clk) tbd ns rising edge to rising edge minimum hold time (io_update to sync_clk) 0 ns rising edge to rising edge minimum setup time (profile inputs to sync_clk) tbd ns minimum hold time (profile inputs to sync_clk) 0 ns data latency (pipe line delay) pipeline delays for freq, phase, amp changes are programmable to match one another. matched pipe line of freq, phase, amplitude tbd sys clks matched frequency word to dac output tbd sys clks unmatched phase offset word to dac output tbd sys clks unmatched amplitude word to dac output tbd sys clks unmatched cmos logic inputs v ih 2.2 v v il 0.6 v logic 1 current 3 12 ua logic 0 current -12 ua input capacitance 2 pf cmos logic outputs (1 ma load) v oh 2.8 v v ol 0.4 v power supply total power dissipation- all channels on, single-tone mode tbd mw maximum power dissipation- all channels, freq accumulator output multiplier on tbd iavdd C all channels on, single tone mode tbd ma iavdd C all ch(s) on, freq accum, and output multiplier on tbd ma idvdd C all ch(s) on, single tone mode tbd ma idvdd C all ch(s) on, freq accum, and output multiplier on tbd ma idvdd_i/o tbd ma power down mode tbd ma
preliminary technical data AD9959 rev. prb | page 5 of 9 absolute maximum ratings table 2. parameter rating maximum junction temperature 150c dvdd_i/o (pin 49) 4 v avdd, dvdd 2 v digital input voltage (dvdd_i/o = 3.3 v) C0.7 v to +4v digital output current 5 ma storage temperature C65c to +150c operating temperature C40c to +105c lead temperature (10 sec soldering) 300c ja 21c/w jc 2c/w stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating on ly and functional operation of the device at these or any other conditions above those indicated in the operational section of this sp ecification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. iout iout input output dvdd_i/o= 3.3v terminate outputs into avdd. do not exceed output voltage compliance. avoid overdriving digital inputs. forward biasing diodes may couple digital noise on power pins. 1.5 k 1.5 k ref_clk ref_clk zz avdd ref_clk inputs are internally biased and need to be ac-coupled. osc inputs are dc coupled cmos digital inputs dac ouputs osc / ref_clk inputs amp osc osc avdd avdd figure 1 equivalent input and output circuits
AD9959 preliminary technical data rev. prb | page 6 of 9 product overview the AD9959 consists of four independently programmable dds channels. the AD9959 features independent frequency, phase, and amplitude control of each channel; this allows for the correction of imbalances due to analog processing such as filtering, amplification, or pcb layout related mismatches. the AD9959 supports frequency sweeping for radar and instrumentation applications. since all four channels share a common system clock, they are inherently synchronized. if more than four channels are required, synchronizing multiple AD9959s is a simple task. the AD9959 uses advanced dds technology which provides low power dissipation with high performance. the device incorporates four integrated high speed 10-bit dacs with excellent wideband and narrowband sfdr. each dds has a 32- bit frequency tuning word, 14-bits of phase offset, and a 10-bit output scale multiplier. each dac has it own programmable reference to enable a different full scale current for each channel. each dds acts as a high resolution frequency divider with the ref_ clk as the input and the dac providing the output. the ref_clk input source is common to all dds channels, and can be driven directly, or used in combination with an integrated ref_clk multiplier (using a pll) up to a maximum of 500 msps. the ref_ clk multiplication factor is programmable from 4 to 20, in integer steps. the ref_clk input features an oscillator which supports either a crystal as a source, or may be bypassed. the crystal frequency must be between 20mhz and 30mhz. the crystal can be used with or without the ref_clk multiplier. the dac outputs are supply referenced and must be terminated into avdd by a resistor, or an avdd center-tapped transformer. the AD9959 comes in a space-saving 56-lead lfcsp package. the dds core (avdd and dvdd pins) must be powered by a 1.8v supply. the digital i/o interface (spi) operates at 3.3v and requires that the pin labeled dvdd_i/o (pin 49) be connected to 3.3v. the AD9959 operates over the industrial temperature range of -40c to +85
preliminary technical data AD9959 rev. prb | page 7 of 9 pin configuration top view (not to scale) 17 22 23 24 25 26 27 28 18 19 20 21 16 15 30 31 32 33 34 35 36 37 41 40 39 38 29 42 54 49 dvdd dgnd 48 47 46 45 44 43 53 52 51 50 55 56 clk_mode_sel 5 4 3 2 11 12 13 avdd agnd pwr_dwn_ctl 9 8 7 6 14 1 agnd avdd dac_rset avdd avdd agnd ch1_iout ch1_iout avdd avdd ch0_iout ch0_iout agnd avdd agnd agnd 10 sdio_1 sdio_2 sdio_3 dgnd dvdd i/o_update sync_in sync_clk master_reset avdd agnd avdd ch2_iout ch2 _iout agnd agnd ch3_iout ch3_iout avdd agnd osc / ref_clk osc / ref_clk sync_out agnd avdd loop_filter p0 p1 p2 p3 dvdd_ i/o cs sclk sdio_0 56-ld lfcsp AD9959 notes : 1) the exposed epad on bottom side of package is an electrical connection and must be soldered to ground. 2) pin 49 is dvdd_io and is tied to 3.3v.
AD9959 preliminary technical data rev. prb | page 8 of 9 table 3. pin function descriptions pin no. mnemonic i/o description 1 sync_in i used to synchronize multiple AD9959s. connect to the sync_out pin of the master AD9959. 2 sync_out o used to synchronize multiple AD9959s. connect to the sync_in pin of the slave AD9959. 3 master_reset i active high reset pin. asserting the reset pin forces the AD9959s internal registers to their default state, as described in the serial i/o port register map section in this document. 4 pwr_dwn_ctl i external power-down control. 5,7,11,15,19,21, 26,31,33,37,39 avdd i analog power supply pins (1.8v). 6,10,12,16,18,20, 25,28,32,34,38 agnd i analog ground pins. 45, 55 dvdd i digital power supply pins (1.8 v). 44, 56 dgnd i digital power ground pins. 8 ch2_iout o true dac output. terminate into avdd. 9 _________ ch2_iout o complementary dac output. terminate into avdd. 13 ch3_iout o true dac output. terminate into avdd. 14 _________ ch3_iout o complementary dac output. terminate into avdd. 17 dac_rset i establishes the reference current for all dacs. a 1.962 k? resistor (nominal) is connected from pin 17 to agnd. 22 osc / ref_clk i complementary reference clock/oscillator inp ut. when the ref_clk is operated in single- ended mode, this pin should be decoupled to avdd or agnd with a 0.1 f capacitor. 23 osc / ref_clk i reference clock/oscillator input. when the ref _clk is operated in single-ended mode, this is the input. 24 clk_mode_sel i control pin for the oscillator section. when high (1.8v), the oscillator section is enabled to accept a crystal as the refclk source. when low, the oscillator section is bypassed. caution: do not drive this pin beyond 1.8v. 27 loop_filter i connect to the external zero compensation network of the pll loop filter for the refclk multiplier. for a 20x multiplier value the network sh ould be a 1.2k? resistor in series with a 1.2 nf capacitor tied to avdd. 29 _________ ch0_iout o complementary dac output. terminate into avdd. 30 ch0_iout o true dac output. terminate into avdd. 35 _________ ch1_iout o complementary dac output. terminate into avdd. 36 ch1_iout o true dac output. terminate into avdd. 40, 41, 42, 43 ps0, ps1, ps2, ps3 i these pins are synchronous to the sync_clk (pin 54). any change in profile inputs transfers the contents of the internal bu ffer memory to the i/o active registers (same as an external i/o _update). 46 i/o_update i a rising edge detected on this pin tran sfers data from serial port buffer to active registers. 47 cs i active low chip select allowing multiple devices to share a common i/o bus (spi). 48 sclk i serial data clock for i/o operations. data bits ar e written on rising edge of sclk and read on the falling edge of sclk. 49 dvdd_i/o i 3.3 v digital power supply for spi port and i/o (excluding clk_mode_sel). 50, 51 52, 53 sdio_0, sdio_1 sdio_2, sdio_3 i/o these data pins have multiple functions. data i/ o pins for the serial i/o port operation. they are also used as data pins in modulation modes . 54 sync_clk o i/o_update and profile signals should meet the set-up and hold requirem ents with respect to this signal in order to guarantee a fixe d pipeline delay of data to dac outputs.
preliminary technical data AD9959 rev. prb | page 9 of 9 esd caution esd (electrostatic discharge) sensitive device. electrosta tic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge with out detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
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